东北大学学报（自然科学版）

东北大学学报(自然科学版) ›› 2006, Vol. 27 ›› Issue (9): 968-971.DOI: -

• 论著 • 上一篇    下一篇

一种嵌入式硬件多线程处理器的研究

尹震宇;赵海;张文波;王小英;   

  1. 东北大学信息科学与工程学院;东北大学信息科学与工程学院;东北大学信息科学与工程学院;东北大学信息科学与工程学院 辽宁沈阳110004;辽宁沈阳110004;辽宁沈阳110004;辽宁沈阳110004
  • 收稿日期:2013-06-23 修回日期:2013-06-23 出版日期:2006-09-15 发布日期:2013-06-23
  • 通讯作者: Yin, Z.-Y.
  • 作者简介:-
  • 基金资助:
    国家高技术研究发展计划项目(2001AA415320)

Implementation of a hardware-scheduled multithread processor for embedded system

Yin, Zhen-Yu (1); Zhao, Hai (1); Zhang, Wen-Bo (1); Wang, Xiao-Ying (1)   

  1. (1) School of Information Science and Engineering, Northeastern University, Shenyang 110004, China
  • Received:2013-06-23 Revised:2013-06-23 Online:2006-09-15 Published:2013-06-23
  • Contact: Yin, Z.-Y.
  • About author:-
  • Supported by:
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摘要： 提出了一种基于同时多线程技术的硬件多线程处理器设计.通过处理器内部的硬件机制来完成对多线程的调度管理,实现基于硬件的时间片轮询多线程调度机制.最大程度地减少操作系统中关于线程调度的开销,提高处理器执行多用户线程时的整体效率,简化了用户在多线程条件下的编程复杂度,增强了多线程运行环境下处理器对线程的保护.

关键词: 多线程处理器, 多线程处理, FPGA, 嵌入式系统, 处理器设计

Abstract: Taking account of the advantages and disadvantages of the existing software-based multithread scheduling for embedded system, a hardware-based design of multithread processor is proposed to implement simultaneously the multithread switching by polling through time slice. Thus, the scheduling cost for operating system can be minimized with the overall efficiency of the processor improved during the multithread execution, and the users' programming complexity can also be reduced under multithread conditions with the processor offering more powerfully protection for the threads during multithread running.

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