Abstract: A two-cores embedded processor (TEP) model was proposed to overcome the problems of slow processing speed and the limited main frequency ascension of the embedded mononuclear processor. On the basis of the nonuniform storage structure, the simulated distributed storage structure was presented to solve reliance and distribution of memory when the processor is running. The arbitration mechanism of the subordinate unit was proposed to realize the access of sharing resources for the accessing memory problem of the share data storage among multiple processors. On the basis of the separation of the message data, a kind of data transmission scheme was proposed to overcome a large number of the data transmission and the higher communication spending of the multiple processors facing the multimedia applications. The system was realized and verified on the FPGA platform, which indicated that TEP got a good performance on accelerator with less resource/transmission spending.