Abstract: In the network security system, there is a limitation on the speed of software-based packet classification due to the processor performance, the serial program execution and so on. In order to improve the speed of packet classification and pre-processing for rules, and adapt to the rules updated quickly, a packet classification system based on FPGA was designed and implemented using hardware circuit and the binary tree structure generated through the pre-processing for rules. The experimental results show that the pre-processing time for 50000 rules is shorter than 0.051 s, the average speed of packet classification is bigger than 10 Gbit/s and the average speed of rule-header classification for Snort IDS is bigger than 20 Gbit/s.