LI Zhen-ni， LI Jing-jiao， WANG Ai-xia， ZHANG Ren-shen. A New Network-on-Chip Topology and Its Adaptive Routing Algorithm[J]. Journal of Northeastern University Natural Science, 2017, 38(9): 1217-1221.
[1]李贞妮，李晶皎，方志强，等.异步2D-Torus片上网络自适应路由算法［J］.东北大学学报(自然科学版)，2015，36(9):1217-1221.(Li Zhen-ni，Li Jing-jiao，Fang Zhi-qiang，et al.Adaptive routing algorithm of asynchronous 2D-Torus network-on-chip ［J］.Journal of Northeastern University (Natural Science)，2015，36(9):1217-1221.) [2]王新玉，向东，虞志刚.TM:一种新的片上网络拓扑结构［J］.计算机学报，2014，37(11):2327-2341.(Wang Xin-yu，Xiang Dong，Yu Zhi-gang.TM:a new topology for networks-on-chip ［J］.Chinese Journal of Computers，2014，37(11):2327-2341.) [3]Xu Y，Zhao B，Zhou X，et a1.A low-radix and low-diameter 3D interconnection network design ［C］// Proceedings of the International Symposium on High Performance Computer Architecture.Raleigh，2009:30-42. [4]Taylor M B，Lee W，Miller J，et al.Evaluation of the raw microprocessor:an exposed-wire-delay architecture for ILP and streams ［C］// Proceedings of the 31st Annual International Symposium on Computer Architecture.Munich，2004:2-13. [5]Moraes F，Calazans N，Mello A，et al.Hermes:an infrastructure for low area overhead packet-switching networks on chip ［J］.Integration，the VLSI Journal，2004，38(1):69-93. [6]Dally W J，Towles B.Route packets，not wires:on-chip interconnection networks ［C］//Proceedings of the 38th Design Automation Conference.New York，2001:684-689. [7]Gul K S，Hamza M M，Khan S A，et al.Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees ［J］.PLoS One，2015，10(4):1-17. [8]Feero B，Pande P.Performance evaluation for three-dimensional networks-on-chip ［C］//IEEE Computer Society Annual Symposium on VLSI.Porto Alegre，2007:305-310. [9]Chiu G M.The odd-even turn model for adaptive routing ［J］.IEEE Transactions on Parallel and Distributed Systems，2000，11(7):729-738. [10]Touzene A，Day K.All-to-all broadcasting in torus network on chip ［J］.The Journal of Supercomputing，2015，71(7):2585-2596. [11]Ren P J，Kinsy M A，Zheng N N.Fault-aware load-balancing routing for 2D-Mesh and torus on-chip network topologies ［J］.IEEE Transactions on Computers，2016，65(3):873-887. [12]周磊，吴宁，李云.一种基于2D-Mesh的片上网络无死锁容错路由算法［J］.上海交通大学学报，2013，47(1):18-22.(Zhou Lei，Wu Ning，Li Yun.A fault-tolerant and deadlock-free routing algorithm in 2D-Mesh for network on chip ［J］.Journal of Shanghai Jiao Tong University，2013，47(1):18-22.)
